1. Field of the Invention
The present invention relates generally to low frequency component restoration circuits, and more particularly, to a low frequency component restoration circuit for restoring and compensating for a low frequency component of a digital signal when the low frequency component, including direct current, is lost in a digital signal transmission, recording or reproducing system such as a digital video tape recorder (referred to as digital VTR, hereinafter).
2. Description of the Background Art
Conventionally, a binary (0, 1 or +1, -1) digital signal such as an NRZ (Non-Return-to-Zero) signal comprises a low frequency component including a direct current component. FIG. 1 is a diagram showing frequency characteristics of such a digital signal, where the axis of abscissa represents a relative frequency and the axis of ordinate represents a relative level. In FIG. 1, a solid line represents frequency characteristics of the above described digital signal comprising a low frequency component. In transmitting, recording or reproducing the digital signal, a signal component in the low frequency region, which is represented by a broken line, may be cut off for the following reasons.
More specifically, in case of signal transmission through, for example, a transmission path, the transmission of a digital signal and the supply of power may be simultaneously made using a pair of signal lines. In such a case, a low frequency component in the digital signal may be cut off to transmit a signal having a frequency component higher than a given value, and a low frequency region including a DC (Direct Current) region may be allocated to the supply of power.
In addition, in case of recording and reproducing of the digital signal of, for example, a VTR, the low frequency component of the digital signal is lost due to differential response characteristics of a magnetic head.
As described in the foregoing, when the low frequency region of the digital signal is cut off, a base line of the digital signal wanders. Such a wandering of a base line is called "base line wandering".
FIG. 2 is a waveform diagram showing a digital signal having its base line wandering, where a solid line represents a waveform of the digital signal and a dot and dash line represents the base line thereof. If and when the base line wanders as shown in FIG. 2, it becomes difficult to precisely determine whether the digital signal is at a high level or a low level on a receiving or reproducing side of the digital signal. As a result, the possibility is increased that a code error occurs.
Therefore, conventionally, on the receiving or reproducing side of the digital signal, a DC restoration circuit employing a so-called quantized feedback method is utilized in order to compensate for the low frequency component which is lost in the digital signal as described above. Such a DC restoration circuit is disclosed in, for example, Japanese Patent Laying-Open No. 60-129975.
FIG. 3 is a schematic block diagram showing one example of such a conventional DC restoration circuit, and FIG. 4 is a diagram showing frequency characteristics of the circuit shown in FIG. 3. In FIG. 4, the axis of abscissa represents a relative frequency and the axis of ordinate represents a relative level, as in FIG. 1.
In FIG. 3, a digital signal having a frequency component represented by a solid line of FIG. 4 is input to an input terminal 1 from a predetermined transmission or reproducing system (for example, a magnetic head of a digital VTR). This digital signal corresponds to a signal having its low frequency region, represented by the broken line of FIG. 1, cut off, out of the inherent frequency component represented by the solid line of FIG. 1 from the above described various causes. This digital signal is supplied to one input terminal 3 of an adder 2. In addition, an output terminal 4 of the adder 2 is connected to an input of a data determination circuit 5. This determination circuit 5 performs processing such a waveform-shaping and data detection with respect to an inputted signal. A data signal "1" or "0" is output from an output terminal 8. Described in more detail, this data determination circuit 5 is constituted such that a timing clock is extracted from the input digital signal and the input digital signal is latched by the extracted timing clock to take out a binary signal "0" or "1". Out of thus output data signal, a low frequency component extracted by a low-pass filter (LPF) 6 is supplied to the other input terminal 7 of the adder 2 as a feedback signal. It is assumed that pass characteristics of the LPF 6 are set to be approximately equal to low frequency cut-off characteristics of the digital signal supplied to the input terminal 1. As a broken line in FIG. 4 is extracted from the LPF 6 and added to the input signal by the adder 2, so that the lost low frequency component in the input digital signal is restored.
Meanwhile in the conventional DC1restoration circuit as shown in FIG. 3, the feedback value from the LPF 6 is always constant. Accordingly, in the case of recording and reproducing of the digital signal in, for example, the digital VTR, if the amplitude of the input digital signal wanders due to spacing loss, drop out or the like, a balance between a compensation signal from the LPF 6 and a signal to be compensated from the input terminal 1 is destroyed because the feedback value is constant as described above, so that stable compensation for a low frequency component cannot be made.
FIG. 5 is a diagram showing one example of a DC restoration circuit proposed to solve such a problem, which is disclosed in, for example, Japanese Patent Laying-Open No. 61-123064. The DC restoration circuit shown in FIG. 5 is the same as that shown in FIG. 3 except for the following. Namely, a variable gain amplifier 9 is provided between an LPF 6 and an input terminal 7 of an adder 2. In addition, there is provided a level detector 10 for detecting a level of a signal input to an input terminal 1. More specifically, this level detector 10 has a function of rectifying and further smoothing the input signal. The gain of the variable gain amplifier 9, i.e., the feedback value from the LPF 6 is controlled by a control signal from the level detector 10. More specifically, in the DC restoration circuit shown in FIG. 5, the feedback value is controlled corresponding to a level of the input digital signal, so that stable compensation for a low frequency component can be made. FIG. 6 is a waveform diagram showing one example of an input signal of the DC restoration circuit of FIG. 5. Described in more detail, FIG. 6 (a) represents a normal level wandering of an input signal, for example, a relatively moderate level wandering caused in every scan period of a rotary magnetic head, i.e., every one field, in a digital VTR. Such a moderate level wandering is caused due to error of a tracking, difference in touching of a tape to a head (head touch) when the rotary magnetic head starts coming in contact with a magnetic tape and leaving the same. In the DC restoration circuit shown in FIG. 5, since the feedback value is controlled in accordance with the level wandering of the entire input signal, as described above, the level detector 10 fully follows a level wandering to precisely control the feedback value of the compensation signal in the case of a moderate level wandering as shown in FIG. 6 (a).
On the contrary, FIG. 6 (b) represents an abrupt level wandering of an input signal caused in a very short period, wherein tape travelling speeds in recording and reproducing differ from each other such as in a high speed search or the like and a rotary magnetic head traverses a plurality of tracks in one scan period to reproduce a signal. In such a case, in the DC restoration circuit of FIG. 5, the level detector 10 cannot follow the abrupt level wandering to cause time delay, resulting in a large error between the compensation signals of the low frequency component. Therefore, in order to make the level detector 10 easily follow the level wandering, a time constant of the level detector should be made smaller However, it is difficult because of waveform distortion, restriction of stability of the system or the like.
In addition, as described above, while the data determination circuit 5 generates a compensation signal based on a digital signal obtained by retiming an input signal by a timing clock extracted from the signal, an amplitude of the input digital signal shown in FIG. 6 (b) becomes zero at a certain point where a phase lock of a PLL circuit (not shown) in the determination circuit 5 for extracting timing clock is unlocked, so that a large error might be caused in the compensation signal during the period where the phase lock is unlocked.